培訓(xùn)方式以講課和實(shí)驗(yàn)穿插進(jìn)行
課程描述:
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課程介紹:
????此課程展現(xiàn)了Incisive設(shè)計(jì)和驗(yàn)證平臺(tái)的從行為級(jí),RTL級(jí)到門級(jí)的完整的設(shè)計(jì)驗(yàn)證流程,本課程主要是針對(duì)具有集成電路設(shè)計(jì)和驗(yàn)證基本知識(shí)的設(shè)計(jì)或驗(yàn)證工程師而準(zhǔn)備。通過(guò)本課程的培訓(xùn)使用戶對(duì)Cadence的驗(yàn)證方法和工具使用有一個(gè)全面、整體概念,用戶在實(shí)際工作中能根據(jù)所掌握的概念和方法,應(yīng)用先進(jìn)的驗(yàn)證方法提高集成電路的驗(yàn)證效率和質(zhì)量。
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Incisive??設(shè)計(jì)驗(yàn)證平臺(tái)介紹:
????要獲得今天的復(fù)雜集成電路功能驗(yàn)證所需的速度和效率要求我們采用一體化的驗(yàn)證方法。Cadence Incisive平臺(tái)適用于從系統(tǒng)設(shè)計(jì)到系統(tǒng)內(nèi)設(shè)計(jì)的所有設(shè)計(jì)驗(yàn)證領(lǐng)域 – 嵌入式軟件、控制、數(shù)據(jù)通路、模擬/數(shù)字混合信號(hào)。
Incisive平臺(tái)是世界上首個(gè)單內(nèi)核驗(yàn)證平臺(tái),Incisive單內(nèi)核架構(gòu)支持Verilog, VHDL, SystemVerilog, SystemC, SCV(SystemC Verification), PSL/Sugar,算法開(kāi)發(fā)和模擬/數(shù)字混合信號(hào)驗(yàn)證。它采用了通用的用戶界面和調(diào)試環(huán)境,支持全事務(wù)級(jí)的驗(yàn)證,一體化測(cè)試方法,按需加速。Incisive平臺(tái)提供業(yè)界最快速,最高效的驗(yàn)證方法。
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課程目標(biāo):
After completing this course, you should be able to:
■?Briefly describe Incisive simulation
■?Set up your environment for Incisive simulation
■?Compile, elaborate, and simulate your design and testbench
■?Debug your design with the textual and graphical interfaces
■?Incorporate components of “foreign” languages in your simulation
■?Annotate SDF timing data to the HDL portions of your design
■?Incorporate C and C++ applications into your simulation
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課程安排:
Unit 1
Time Topic
09:30-09:45??Introduction & agenda
09:45-10:00??Incisive simulation overview
10:00-10:30??Setting up the simulation environment
10:30-12:00??Compiling your design
12:00-13:30??LUNCH
13:30-02:15??Elaborating your design
02:15-03:45??Simulating your design
03:45-05:00??Debugging with the textual interface
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Unit 2
Time Topic
09:30-10:00??Debugging with the textual interface
10:00-11:15??Debugging with the graphical interface
11:15-12:45??Simulating mixed-language designs
12:45-01:45??LUNCH
01:45-02:00??Introducing simulator utilities
02:00-03:30??[optional] Annotating SDF timing
03:30-05:00??[optional] Linking user applications