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1. Cadence PCB 培訓
   一、培訓目標
   高速PCB設計的潮流已經滾滾而來，如何預防PCB板上出現的信號反射、串擾、電源/地平面干擾、時序匹配以及電磁兼容性等一系列新問題好象突然間擋在了您的面前。如何應對新的設計挑戰？Cadence培訓高級班將首先讓您了解這些問題產生的機理，并掌握其解決方法；然后講解并上機練習Cadence的高速?PCB設計與仿真工具SPECCTRAQuest的使用。使您在硬件設計過程中，能夠達到“設計即正確”的目的。
   二、培訓內容：?
   1?高速PCB設計中的理論基礎
   ???? 傳輸線理論、信號完整性（反射、串擾、過沖、地彈、振鈴等）、電磁兼容性和時序匹配等等。
   2?SPECCTRAQuest設計流程
   ???? 2.1?Pre-Placement
   ???? 2.2?Board?Setup?Requirements?for?Extracting?and?Applying?Topologies
   ???? 2.3?Database?Setup?Advisor
   ???????? —Cross-Section
   ???????? —DC?Nets
   ???????? —DC?Voltages
   ???????? —Device?Setup?.???—SI?Models
   ???????? —SI?Audit
   3?拓撲結構的抽取與仿真?Extracting?and?Simulating?Topologies
   ????? 3.1?Pre-Route?Extraction?Setup—Default?Model?Selection.
   ???? 3.2?Pre-Route?Extraction?Setup—Unrouted?Interconnect
   ????? 3.3?Pre-Route?Template?Extraction
   ???? 3.4?SQ?Signal?Explorer?Expert
   ???? 3.5?Analysis?Preferences
   ???? 3.6?SigWave
   ???? 3.7?Delay?Measurements
   4?確定和施加約束?Determining?and?Adding?ConstraintsSolution
   ????? 4.1?Solution?SpaceAnalysis:?Step?1?to?6
   ????? 4.2?Parametric?Sweeps.
   ????? 4.3?Constraints?:
   ???????? Topology?Template?Constraints
   ????????? Switch/Settle?Constraints
   ???????? Assigning?the?Prop?Delay?Constraints
   ???????? Impedance?Constraint
   ???????? Relative?Propagation?Delay?Constraint
   ???????? Diff?Pair?Constraints
   ???????? Max?Parallel?Constraint
   ???????? Wiring?Constraint
   ???????? User-Defined?Constraint
   ???????? Signal?Integrity?Constraints
   ???? 4.4?Usage?of?Constraints?Defined?in?Topology?Template
   5?模板應用和基于約束的布局
   ???? Template?Applications?and?Constraint-Driven?Placement
   ???? 5.1?Creating?a?Topology
   ???? 5.2?Wiring?the?Topology
   ???? 5.3?TLines?and?Trace?Models
   ???? 5.4?Coupled?Traces
   ???? 5.5?RLGC?Matrix?of?Coupled?Trace?Models
   ???? 5.6?Crosstalk?Simulation?in?SQ?Signal?Explorer?Expert
   ???? 5.7?Simulating?with?Coupled-Trace?Models
   ???? 5.8?Sweep?Simulation?Results?with?Coupled-Trace?Models
   ???? 5.9?Extracting?a?Topology?Using?the?Constraint?Manager
   ???? 5.10?Electrical?Constraint?Set
   ???? 5.11?Applying?Electrical?CSet
   ???? 5.12?Worksheet?Analysis
   ???? 5.13?Spacing?and?Physical?Rule?Sets
   ???? 5.14?Electrical?Rule?Set
   6?基于約束的布線?Constraint-Driven?Routing
   ???? 6.1?Manual?Routing
   ???? 6.2?Routing?with?the?SPECCTRA?Smart?Route
   ???? 6.3?Driving?Constraints?in?Routing
   7?布線后的DRC檢查和分析?Post-Route?DRC?and?Analysis
   ???? 7.1?Post-Route?Analysis
   ???? 7.2?SigNoise
   ???? 7.3?Reflection?Simulation
   ???? 7.4?Reflection?Waveform?Analysis
   ???? 7.5?Comprehensive?Simulation
   ???? 7.6?Crosstalk?Simulation
   ???? 7.7?Crosstalk?Analysis
   ???? 7.8?Simultaneous?Switching?Noise?Simulation
   ???? 7.9?SSN?Waveform?Analysis
   ???? 7.10?System-Level?Analysis
   ???? 7.11?A?Complete?Design?Link
   ???? 7.12?Initialize?Design?Link
   8?差分信號設計?Differential?Pair?Design?Exploration
   ???? 8.1?Types?of?Differential?Pairs?in?SPECCTRAQuest
   ???? 8.2?Create?Differential?Pair?Using?SPECCTRAQuest
   ???? 8.3?Create?Differential?Pair?Using?Constraint?Manager
   ???? 8.4?Assigning?Differential?Pair?Signal?Models
   ???? 8.5?Preference?to?Extract?Unrouted?Differential?Pair?Topology
   ???? 8.6?Extracting?Unrouted?Differential?Pair?Topology
   ???? 8.7?Custom?Stimulus?to?Analyze?Differential?Pair?Topology
   ???? 8.8?Differential?Pair?Topology?Analysis
   ???? 8.9?Coupled?Trace?Model?and?Differential?Pair?Topology
   ???? 8.10?Layout?Cross-section?Editor
   ???? 8.11?Differential?Pair?Constraints
   ???? 8.12?Differential?Pair?Constraints?in?the?Constraint?Manager
   ???? 8.13?Differential?Pair?Analysis?in?the?Constraint?Manager
   ???? 8.14?Post?Route?Extraction
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